1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to a substrate-triggered ESD protection circuit by using triple-well.
2. Description of the Prior Art
With the continued scaling down of semiconductor integrated circuit (IC) devices, the present trend is moving towards production of semiconductor integrated circuits having very small sizes in the advanced sub-quarter-micron CMOS technologies. It is consequently increasingly important to build electrostatic discharge (ESD) protection circuits on the chip to protect the devices and circuits of the IC against ESD-related damage. The ESD robustness of commercial IC products is generally needed to be higher than 2 kV in the human-body-model (HBM) ESD stress. While withstanding ESD overstress, it is desired that the on-chip ESD protection circuits have relatively small dimensional requirements to save silicon area. With respect to this issue, heat dissipation issues become paramount. In the present, the efficiency and performance of the substrate-trigger ESD protection circuits is better than other type ESD protection circuits.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a structure diagram of a substrate-triggered ESD protection circuit 10 according to the prior art. FIG. 2 is a circuit diagram of the ESD protection circuit 10 shown in FIG. 1. The ESD protection circuit 10 is formed on a P-type substrate 12 and comprises a resistor T, a capacitor C, an inverter 30, a substrate resistor Rsub, a parasitic lateral n-p-n bipolar junction transistor (BJT) 36, and a NMOS transistor 38. The resistor R and the capacitor C are connected in series between a first power terminal VDD and a second power terminal VSS. The inverter 30 is connected to the first power terminal VDD and the second power terminal VSS. An input terminal of the inverter 30 is connected to the resistor R and the capacitor C, and an output terminal VB of the inverter 30 is connected to the substrate resistor Rsub and a base of the parasitic lateral n-p-n BJT 36, where the substrate resistor Rsub is an equivalent resistor between the p+ diffusion region 14 and the second power terminal VSS. The NMOS 38 comprises a doped polysilicon gate 24, a drain formed by an n+ diffusion region 16, and a source formed by another n+ diffusion region 18. The drain 16 is connected to the first power terminal VDD, and the gate 24 and the source 18 are connected to the second power terminal VSS. The parasitic lateral n-p-n BJT 36 underneath the NMOS transistor 38 is triggered by a trigger current conducting from the P+ diffusion region 14 to the first power terminal VSS. A plurality of hallow trench isolation (STI) structures 26 are used to isolate each NMOS transistor 38 from other electrical devices. Moreover, two N-wells 20 are formed under the sources 18 of the NMOS transistors 38, and a p+ diffusion region 22 in the P-type substrate 12 is connected to the second power terminal VSS.
As an ESD phenomenon of the ESD protection circuit 10 occurs, a positive pulse is applied to the first power terminal VDD. While the capacitor C is charged by the ESD, a voltage level of the input terminal of the inverter 30 is pulled up. The voltage level of the input terminal of the inverter 30, hence, is at a low state when the ESD phenomenon begins. Therefore, the PMOS transistor 32 is turned on so that an ESD current flows from the PMOS 32 through the output terminal of the inverter 30 and the substrate resistor Rsub to the second power terminal VSS. Because of the current flowing through the substrate resistor Rsub, the voltage level of the output terminal of the inverter 30 is pulled up. While the voltage level of the output terminal of the inverter 30 is pulled up to a predetermined level, the parasitic lateral n-p-n BJT 36 is turned on so that another ESD path, i.e. form the parasitic lateral n-p-n BJT 36 to the second power terminal VSS, is generated. The inputted ESD, thus, can pass through the ESD path. However, when the ESD phenomenon of the ESD protection circuit 10 begins, the parasitic lateral n-p-n BJT 36 is not turned on until the voltage gap between the two ends of the substrate resistor Rsub exceeds the predetermined level, so the turn-on efficiency of the ESD protection circuit 10 is not ideal.
Please refer to FIG. 3 and FIG. 4. FIG. 3 is a structure diagram of another substrate-triggered ESD protection circuit 50 according to the prior art. FIG. 4 is a circuit diagram of the ESD protection circuit 50 shown in FIG. 4. The ESD protection circuit 50 is formed on a P-type substrate 52 and comprises a resistor T, a capacitor C, two inverters 30, a PMOS transistor 74, and two parasitic lateral p-n-p BJTs 76 and 78. Similar to the ESD protection circuit 10, in the ESD protection circuit 50, the resistor R and the capacitor C are connected in series between the first power terminal VDD and the second power terminal VSS. The inverters are connected to the first power terminal VDD and the second power terminal VSS. An input terminal of the left inverter 30 is connected to the resistor R and the capacitor C, and an output terminal VB of the right inverter 30 is connected to bases of the two parasitic lateral p-n-p BJTs 76 and 78. The PMOS transistor 74 is formed in a N-well 54 and comprises a doped polysilicon gate 64, a source formed by an p+ diffusion region 58, and a drain formed by another p+ diffusion region 60. The source 58 is connected to the first power terminal VDD, the gate 64 is connected to the output terminal VB of the right inverter 30, and the drain 60 is connected to the second power terminal VSS. The parasitic lateral p-n-p BJT 76 is composed of the p+ diffusion region 58, the N-well 54, and the p+ diffusion region 60, and the parasitic lateral p-n-p BJT 78 is composed of the p+ diffusion region 58, the N-well 54, and the P-type substrate 52. A plurality of hallow trench isolation (STI) structures 66 are used to isolate each PMOS transistor 74 from other electrical devices. Moreover, a p+ diffusion region 62 in the P-type substrate 52 is connected to the second power terminal VSS.
As an ESD phenomenon of the ESD protection circuit 50 occurs, a positive pulse is applied to the first power terminal VDD. While the capacitor C is charged by the ESD, a voltage level of the input terminal of the left inverter 30 is pulled up. Hence, when the ESD phenomenon begins, the voltage level of the input terminal of the left inverter 30 and the voltage level of the output terminal of the right inverter 30 are both at a high state. Meanwhile, the gate 64 of the PMOS transistor 74 and the bases of the two parasitic lateral p-n-p BJTs 76 and 78 are at a low state. Because the first power terminal VDD is applied by a positive ESD voltage, the channel of the PMOS transistor is turned on and a PN junction is formed between the p+ diffusion region 58 and the N-well 54 that results in turning on of the two parasitic lateral p-n-p BJTs 76 and 78. Therefore, the ESD currents respectively flow from the first power terminal VDD through the channel of the PMOS transistor 74 and the two parasitic lateral p-n-p BJTs 76 and 78 to the second power terminal VSS. The PMOS transistor 74 and the two parasitic lateral p-n-p BJTs 76 and 78 are turned on immediately when the positive pulse is applied to the first power terminal VDD, so the turn-on efficiency of the ESD protection circuit 50 is better than that of the ESD protection circuit 10. However, because the mobility of holes is less than the mobility of electrons, the discharge performance of the ESD protection circuit 50 is worse than that of the ESD protection circuit 10.